3.3v, 125-mhz, multi-output zero delay buffer cy29977 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07414 rev. *a revised december 27, 2002 77 features ? output frequency up to 125 mhz supports powerpc ? and pentium ? processors 12 clock outputs: frequency configurable configurable output disable two reference clock inputs for dynamic toggling oscillator or crystal reference input spread spectrum compatible glitch-free output clocks transitioning 3.3v power supply industrial temperature range: ? 40 c to +85 c 52-pin tqfp package note: 1. x = the reference input frequency, 200 mhz < f vco < 480 mhz. . table 1. frequency table [1] vc0_sel fb_sel2 fb_sel1 fb_sel0 f vco 00008x 000112x 001016x 001120x 01008x 010112x 011016x 011120x 10004x 10016x 10108x 101110x 11004x 11016x 11108x 111110x block diagram pin configuration ref_sel 0 1 0 1 phase detector vco lpf sync frz d q qa0 sync frz d q sync frz d q sync frz d q sync frz d q sync frz d q power-on reset output disable circuitry data generator /2, /6, /4, /12 /2, /6, /4, /10 /8, /2, /6, /4 /4, /6, /8, /10 sync pulse xin xout tclk0 tclk1 tclk_sel fb_in mr#/oe sela(0,1) 2 selb(0,1) 2 selc(0,1) 2 fb_sel(0:2) 3 sclk sdata inv_clk qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 fb_out sync 12 vco_sel pll_en vss mr#/oe sclk sdata fb_sel2 pll_en ref_sel tclk_sel tclk0 tclk1 xin xout vdd fb_sel1 sync vss qc0 vddc qc1 selc0 selc1 qc2 vddc qc3 vss inv_clk selb1 selb0 sela1 sela0 qa3 vddc qa2 vss qa1 vddc qa0 vss vco_sel vss qb0 vddc qb1 vss qb2 vddc qb3 fb_in vss fb_out vddc fb_sel0 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 cy29977
cy29977 document #: 38-07414 rev. *a page 2 of 9 note: 2. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power (<0.2 ? ). if these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces . pin description [2] pin no. pin name pwr i/o type description 11 xin i pu oscillator input. connect to a crystal 12 xout i pd oscillator output. connect to a crystal 9 tclk0 i pu external reference/test clock input. 10 tclk1 i pu external reference/test clock input. 44, 46, 48, 50 qa(3:0) vddc o clock outputs. see table 2 for frequency selections. 32, 34, 36, 38 qb(3:0) vddc o clock outputs. see table 2 for frequency selections. 16, 18, 21, 23 qc(3:0) vddc o clock outputs. see table 2 for frequency selections. 29 fb_out vddc o feedback clock output. connect to fb_in for normal operation. the divider ratio for this output is set by fb_sel(0:2). see table 1 . a bypass delay capacitor at this output will control input refer- ence/output banks phase relationships. 25 sync vddc o synchronous pulse output. this output is used for system syn- chronization. the rising edge of the output pulse is in sync with both the rising edges of qa (0:3) and qc(0:3) output clocks regardless of the divider ratios selected. 42, 43 sela(1,0) i pu frequency select inputs. these inputs select the divider ratio at qa(0:3) outputs. see table 2 . 40, 41 selb(1,0) i pu frequency select inputs. these inputs select the divider ratio at qb(0:3) outputs. see table 2 . 19, 20 selc(1,0) i pu frequency select inputs. these inputs select the divider ratio at qc(0:3) outputs. see table 2 . 5, 26, 27 fb_sel(2:0) i pu feedback select inputs. these inputs select the divide ratio at fb_out output. see table 1 . 52 vco_sel i pu vco divider select input. when set low, the vco output is divid- ed by 2. when set high, the divider is bypassed. see table 1 . 31 fb_in i pu feedback clock input. connect to fb_out for accessing the pll. 6 pll_en i pu pll enable input. when asserted high, pll is enabled. when low, pll is bypassed. 7 ref_sel i pu reference select input. when high, the pecl clock is selected. when low, tclk (0,1) is the reference clock. 8 tclk_sel i pu tclk select input. when low, tclk0 is selected and when high tclk1 is selected. 2mr#/oe ipu master reset/output enable input. when asserted low, resets all of the internal flip-flops and also disables all of the outputs. when pulled high, releases the internal flip-flops from reset and enables all of the outputs. 14 inv_clk i pu inverted clock input. when set high, qc(2,3) outputs are inverted. when set low, the inverter is bypassed. 3sclk ipu serial clock input. clocks data at sdata into the internal register. 4sdata ipu serial data input. input data is clocked to the internal register to enable/disable individual outputs. this provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 vddc 3.3v power supply for output clock buffers. 13 vdd 3.3v supply for pll 1, 15, 24, 30, 35, 39, 47, 51 vss common ground
cy29977 document #: 38-07414 rev. *a page 3 of 9 description the cy29977 has an integrated pll that provides low-skew and low-jitter clock outputs for high-performance microproces- sors. three independent banks of four outputs as well as an independent pll feedback output, fb_out, provide excep- tional flexibility for possible output configurations. the pll is ensured stable operation given that the vco is configured to run between 200 mhz to 480 mhz. this allows a wide range of output frequencies up to125 mhz. the phase detector compares the input reference clock to the external feedback input. for normal operation, the external feedback input, fb_in, is connected to the feedback output, fb_out. the internal vco is running at multiples of the input reference clock set by fb_sel(0:2) and vco_sel select in- puts, refer to table 1 for a frequency table. the vco frequen- cy is then divided down to provide the required output frequen- cies. these dividers are set by sela(0,1), selb(0,1), selc(0,1) select inputs, see table 2 below. for situations were the vco needs to run at relatively low frequencies and hence might not be stable, assert vco_sel low to divide the vco frequency by 2. this will maintain the desired output re- lationships, but will provide an enhanced pll lock range. the cy29977 is also capable of providing inverted output clocks. when inv_clk is asserted high, qc2 and qc3 output clocks are inverted. these clocks could be used as feedback outputs to the cy29977 or a second pll device to generate early or late clocks for a specific design. this inversion does not affect the output to output skew. table 2. vco_sel sela1 sela0 qa selb1 selb0 qb selc1 selc0 qc 0 0 0vco/40 0vco/40 0vco/16 0 0 1 vco/12 0 1 vco/12 0 1 vco/4 0 1 0vco/81 0vco/81 0vco/12 0 1 1 vco/24 1 1 vco/20 1 1 vco/8 1 0 0vco/20 0vco/20 0vco/8 1 0 1vco/60 1vco/60 1vco/2 1 1 0vco/41 0vco/41 0vco/6 1 1 1 vco/12 1 1 vco/10 1 1 vco/4
cy29977 document #: 38-07414 rev. *a page 4 of 9 zero delay buffer when used as a zero delay buffer the cy29977 will likely be in a nested clock tree application. for these applications the cy29977 offers a low-voltage pecl clock input as a pll ref- erence. this allows the user to use lvpecl as the primary clock distribution device to take advantage of its far superior skew performance. the cy29977 then can lock onto the lvpecl reference and translate with near zero delay to low-skew outputs. by using one of the outputs as a feedback to the pll the prop- agation delay through the device is eliminated. the pll works to align the output edge with the input reference edge, thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. because the static phase off- set is a function of the reference clock, the tpd of the cy29977 is a function of the configuration used. glitch-free output frequency transitions customarily, when output buffers have their internal counters changed ? on the fly. ? their output clock periods will: contain short or ? runt ? clock periods. these are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. contain stretched clock periods. these are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. this device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed ? on the fly ? while it is operating: sela, selb, selc, and vco_sel.
cy29977 document #: 38-07414 rev. *a page 5 of 9 sync output in situations were output frequency relationships are not inte- ger multiples of each other the sync output provides a signal for system synchronization. the cy29977 monitors the rela- tionship between the qa and the qc output clocks. it provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the qa and qc outputs. the duration and the placement of the pulse depend on the higher of the qa and qc output frequencies. the following timing diagram ( figure 1 ) illustrates various waveforms for the sync output. note that the sync output is defined for all possible combinations of the qa and qc outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. sync qc qa sync qc qa sync qa qc sync qc qa sync qa qc sync qc qa sync qc qa vco 1:1 mode 2:1 mode 3:1 mode 3:2 mode 4:1 mode 4:3 mode 6:1 mode figure 1.
cy29977 document #: 38-07414 rev. *a page 6 of 9 power management the individual output enable/freeze control of the cy29977 allows the user to implement unique power-management schemes into the design. the outputs are stopped in the logic ? 0 ? state when the freeze control bits are activated. the serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. the qc0 and fb_out outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the loading of the serial data. an output is frozen when a logic ? 0 ? is programmed and enabled when a logic ? 1 ? is written. the enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial ? runt ? clocks. the serial input register is programmed through the sdata input by writing a logic ? 0 ? start bit followed by 12 nrz freeze enable bits. the period of each sdata bit equals the period of the free running sclk signal. the sdata is sampled on the rising edge of sclk. notes: 3. for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal m eets or exceeds these specifications. 4. larger values may cause this device to exhibit oscillator start-up problem. d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0-d3 are the control bits for qa0-qa3, respectively d4-d7 are the control bits for qb0-qb3, respectively d8-d10 are the control bits for qc1-qc3, respectively d11 is the control bit for sync start bit figure 2. table 3. suggested oscillator crystal parameters parameter description conditions min. typ. max. unit t c frequency tolerance note 3 100 ppm t s frequency temperature stability (t a - 10 to +60c) note 3 100 ppm t a aging (first 3 years @ 25c) note 3 5 ppm/yr cl load capacitance the crystal ? s rated load. note 3 20 pf r esr effective series resistance (esr) note 4 40 80 ohms
cy29977 document #: 38-07414 rev. *a page 7 of 9 maximum ratings [5] input voltage relative to v ss :............................. vss ? 0.3v input voltage relative to v dd : ............................. v dd + 0.3v storage temperature: ................................ ? 65 c to + 150 c operating temperature: ................................ ? 40 c to +85 c maximum power supply: ................................................5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any volt- age higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd unused inputs must always be tied to an appropriate logic volt- age level (either v ss or v dd ). notes: 5. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply srquencing is not required. 6. inputs have pull-up/pull-down resistors that effect input current. 7. driving series or parallel terminated 50 ? (or 50 ? to vdd/2) transmission lines. 8. parameters are guaranteed by design and characterization. not 100% tested in production. 9. maximum and minimum input reference is limited by vc0 lock range. 10. outputs loaded with 30 pf each. 11. 50 ? transmission line terminated into v dd /2. dc parameters: v dd = v ddc = 3.3v 10%, t a = ? 40 c to +85 c parameter description conditions min. typ. max. unit v il input low voltage v ss 0.8 v v ih input high voltage 2.0 v dd v i il input low current (@v il = v ss )note 6 ? 120 a i ih input high current (@v ih = v dd )120 a v ol output low voltage i ol = 20 ma, note 7 0.5 v v oh output high voltage i oh = ? 20 ma, note 7 2.4 v i ddc quiescent supply current all v ddc and v dd 10 15 ma i dd pll supply current v dd only 15 ma c in input pin capacitance 4pf ac parameters: [8] v dd = v ddc = 3.3v 10%, t a = ? 40 c to +85 c parameter description conditions min. typ. max. unit tr/tf tclk input rise / fall 3.0 ns fref reference input frequency note 9 note 9 mhz fxtal crystal oscillator frequency see table 3 10 25 mhz frefdc reference input duty cycle 25 75 % fvco pll vco lock range 200 480 mhz tlock maximum pll lock time 10 ms tr/tf output clocks rise / fall time [10] 0.8v to 2.0v 0.15 1.2 ns fout maximum output frequency q ( 2 )125mhz q ( 4 )120 q ( 6 )80 q ( 8) 60 foutdc output duty cycle [10] 45 55 % tpzl, tpzh output enable time [10] (all outputs) 2 10 ns tplz, tphz output disable time [10] (all outputs) 2 8 ns tccj cycle to cycle jitter [10] (peak to peak) 100 ps tskew any output to any output skew [10,11] all outputs at same frequency 350 ps outputs at different frequencies 550 ps tpd propagation delay [11,12] tclk0/1 q fb( 8) ? 270 270 ps
cy29977 document #: 38-07414 rev. *a page 8 of 9 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. 12. tpd is specified for a 50-mhz input reference. tpd is the static phase error of the device and does not include jitter. package drawing and dimensions powerpc is a registered trademark of international business machines. pentium is a registered trademark of intel corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. ordering information part number package name package type production flow CY29977AI a52 52-pin tqfp industrial, -40 c to +85 c 52-lead thin plastic quad flat pack (10x10x1.4 mm) a52 51-85131-**
cy29977 document #: 38-07414 rev. *a page 9 of 9 document title: cy29977 3.3v, 125-mhz, multi-output zero delay buffer document number: 38-07414 rev. ecn no. issue date orig. of change description of change ** 114664 05/17/02 hwt new data sheet *a 122923 12/27/02 rbi add power up requirements to maximum ratings information.
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